A High Precision, Wide Operating Range Charge Pump Circuit in a Phase Locked Loop for a CMOS Image Sensor

Ⅰ. Introduction

Recently, as the demand for high-resolution images in mobile imaging increases, the pixel pitch of a CMOS image sensor(CIS) has been reduced to 0.7μm [1][2]. When the pixel pitch decreases, the amount of incident light decreases, making it difficult to secure the signal-to-noise ratio(SNR) of an image in a low-light environment. Therefore, a recent CIS provides various binning modes that improve sensitivity and SNR by merging some surrounding photodiodes in low-light condition[3][4].

Since the resolution and frame rate of the CIS vary according to the binning mode conditions provided, a wide range of the speed of a main clock used for the CIS is also required. Therefore, a phased locked looop (PLL) circuit of the CIS must be able to generate the main clock in a wide frequency range[5].

The PLL circuit which generates the clock inside the CIS widely uses a charge pump(CP) PLL structure that can easily implement high-speed, low jitter, and wide locking range characteristics[6]. The role of the CP in the PLL is to inject or remove current from the loop filter(LF) to implement the integral operation. One of the key design challenges is to minimize the current mismatch between charge and discharge currents, i.e. current sink and current source. Another design issue, especially in a wideband PLL, is the output voltage headroom of the current source used to implement the CP. To achieve the widest possible clock frequency range, the CP output voltage should ideally remain in the range from ground to the power supply rail. It takes full advantage of the oscillator's tuning range while maintaining current source operation and current invariance.

Therefore, this paper proposes a CP circuit with high precision and wide operating range while decreasing the current mismatch phenomenon for the PLL which generates the clock of the CIS with various binning modes.

Ⅱ. CP Circuit

2.1 CP PLL and Characteristics of CP Circuit

Fig. 1 shows the block diagram of the CP PLL and the schematic diagram of the single-ended CP circuit that is most suitable architecture of the CP for the PLL when considering system flexibility, low power consumption, and silicon area[7]-[9] and the LF circuit.

Fig. 1.

Block diagram of CP PLL and schematic diagram of CP and LF circuits

After receiving the phase difference signal outputs, UP and DN, from the phase frequency detector(PFD), the CP circuit charges or discharges the capacitor of the LF with a constant current during the phase difference signal width to generate the voltage signal, V_CP, and send it to the voltage controlled oscillator (VCO).

The current mismatch and the output voltage headroom of the CP circuit are affected by the output impedances, R_UP and R_DN, and the voltage headrooms, ΔV_HRP and ΔV_HRN, of the current sources, I_UP and I_DN constituting the CP circuit. To design the CP circuit with high precision and wide operating range, I_UP and I_DN should be designed so that the smaller the ΔV_HRP and ΔV_HRN, the larger the R_UP and R_DN[5].

2.2 Conventional CP Circuit

Fig. 2 shows the conventional CP circuit using a cascode current source with a current mirror bias circuit with wide operating range[5]. This structure has high output impedance to minimize current mismatch while having wide operating range by minimizing voltage headroom.

Fig. 2.

Conventional CP circuit implemented and V-I relationship[5]

The output impedances, R_UP and R_DN, of the current sources I_UP and I_DN are obtained by using the impedance reflection rule[10] as follows.

$\[ \begin{array}{c}{R}_{UP}\cong g_{m,{\rm M}UP2}{r}_{ds,{\rm M}UP2}{r}_{ds,{\rm M}UP1}, \hfill \\ R_{DN}\cong g_{m,{\rm M}DN2}{r}_{ds,{\rm M}DN2}{r}_{ds,MDN1}\hfill \end{array} \]$

(1)

Here, g_m,MUP2 and g_m,MDN2 are transconductances of M_UP2 and M_DN2, respectively. Also r_ds,MUP2, r_ds,MUP1, r_ds,MDN2, and r_ds,MDN1 are small-signal equivalent resistances between drain port and source port of M_UP2, M_UP1, M_DN2, and M_DN1, respectively.

Since the CP circuit uses the current mirror bias circuit with wide operating range, its operating range, ΔV_{CP_Swing} is obtained as follows[10].

$\[ \begin{array}{c}\Delta V_{HRN}\le \Delta V_{{CP}_{-}Swing}\le V_{DD}-\Delta V_{HRP}\hfill \\ \Delta V_{HRN}=V_{OV,MDN1}+V_{OV,MDN2},\hfill \\ \Delta V_{HRP}=V_{OV,{\rm M}UP1}+V_{OV,{\rm M}UP2}\hfill \end{array} \]$

(2)

Here, V_OV,MDN1, V_OV,MDN2, V_OV,MUP1, and V_OV,MUP2 are overdrive voltages of M_DN1, M_DN2, M_UP1, and M_UP2, respectively.

2.3 Proposed CP Circuit

Fig. 3 shows the proposed high precision, wide operating range CP circuit. By applying the regulated cascode structure composed of the operational transconductance amplifiers(OTAs), OTA_N and OTA_P, R_UP and R_DN of I_UP and I_DN increase when compared to Eq. (1) as follows[10].

$\[ \begin{array}{c}{R}_{UP}\cong A_{OTAN}{g}_{m,{\rm M}UP2}{r}_{ds,{\rm M}UP2}{r}_{ds,{\rm M}UP1}, \hfill \\ R_{DN}\cong A_{OTAP}{g}_{m,{\rm M}DN2}{r}_{ds,{\rm M}DN2}{r}_{ds,MDN1}\hfill \end{array} \]$

(3)

Fig. 3.

Proposed CP circuit implemented and V-I relationship

Note that A_OTAN and A_OTAP are DC gains of OTA_N and OTA_P, respectively.

Although the regulated cascode structure is used, the operating range of the CP circuit is the same as Eq. (2)[10].

Ⅲ. Experimental Results

3.1 Simulation results

In order to verify the comparison between the conventional CP circuit and the proposed CP circuit, some simulations are performed using 350 nm CMOS process. Here, the MOSFET sizes of the current mirror bias circuit and the current source circuit are determined as L_P=0.35 μm, W_P=90 μm (18 μm, m=5), L_N=0.45 μm, W_N=30 μm (6 μm, m=5). The power supply voltage was V_DD=3.3 V and I_CP=100 µA. To implement the regulated cascode architecture for the proposed CP circuit, OTA_N and OTA_P are designed as the differential pair with 5 transistors so that A_OTAN and A_OTAP are 30 V/V.

Fig. 4 shows the simulated I_UP and I_DN graphs while changing the V_CP voltage of each CP circuit. While the magnitude of Δ_{VCP_Swing} of the two CP circuits is the same as 0.4 V, it can be seen that the current sources of the proposed CP circuit have a larger output impedances than those of the conventional CP circuit from the slope of the zoomed-in figures.

Fig. 4.

V-I relationship of CP circuits (X-axis : VCP, Y-axis : IUP & IDN)

Fig. 5 shows the current matching characteristics, I_MIS=I_UP-I_DN, between I_UP and I_DN according to V_CP change obtained by setting UP=1 (UPb=0) and DN=1 (DNb=0) and performing DC analysis on VCP node. From the zoomed-in graph, it can be seen that the I_MIS of the proposed CP circuit is more improved than that of the conventional CP circuit. Considering ΔV_{CP_Swing}=2.5 V, the proposed CP circuit has the maximum current mismatch of 0.22% and the maximum current deviation of 0.17% whereas the conventional CP circuit has the maximum current mismatch of 3.84% and the maximum current deviation of 1.97%. Table 1 shows the summary of the simulation results for CP circuits.

Fig. 5.

Current matching characteristics of CP circuits (X-axis : VCP, Y-axis : IMIS=IUP-IDN)

Table 1.

Summary of simulation results for CP circuits

3.2 Measurement result

Fig. 6 shows the microphotograph of the chip fabricated in 350 nm CMOS process. The power supply voltage is 3.3 V and I_CP is 100 μA.

Fig. 6.

Microphotograph of fabricated chip

The fabricated chip is measured using the source measurement unit of Keithley and the current matching characteristic graph of the CP circuit is obtained as shown in Fig. 7. When ΔV_{CP_Swing}=2.7 V, the maximum current mismatch is 0.31% and the maximum current deviation is 0.19%.

Fig. 7.

Measured current matching characteristics of proposed CP circuit

Ⅳ. Conclusion

In this paper, we proposed the CP circuit with wide operating range while decreasing the current mismatch for the CP PLL generating the clock of the CIS. The operating range and current mismatch of the CP circuit are affected by the characteristics of the current source constituting the CP circuit. The proposed CP circuit is embodied with current mirror bias circuits for wide operating range and current source circuits of regulated cascode structure for high output impedance in order to reduce current mismatch with wide operating range.

The proposed high precision, wide operating range CP circuit is fabricated in a 350 nm CMOS process, and current matching characteristic is measured in the Keithley source measurement unit. The power supply voltage is 3.3 V and the I_CP of the CP circuit is 100 μA. The proposed CP circuit has ΔV_{CP_Swing}=2.7V, where the maximum current mismatch is 0.31% and the maximum current deviation is 0.19%.

Acknowledgments

This research was supported by Kumoh National Institute of Technology (2018-104-129).

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