Design of Interface IP for Automotive I/O Control on SoC FPGA

2.1 ADC modeling

Before modeling the ADC, an Integrated Circuit(IC) is selected and used, and the IC used in this paper is LTC2328. Modeling is performed according to the characteristics of the relevant IC. There is a CNV signal to start ADC operation and a BUSY signal to confirm ADC operation[3]. The input ADC data is 16 bits and operates in accordance with the SCK clock. ADC data is transmitted through Serial Peripheral Interface(SPI). Modeling should be designed to fit the range of maximum and minimum timing values by referring to the data sheet. Check whether the input analog data is linearly converted to digital data by referring to the transfer characteristics. The input voltage range is -10.24 to 10.24V, and the data bits are linear to the applied voltage.

2.2 DAC modeling

The LTC2664 IC is used for DAC modeling. It has four DAC channels, and DAC modeling must also be designed to fall within the timing range by referring to the data sheet. The DAC data output through SPI communication is a total of 24 bits, as shown in Table 1, and consists of 4 command code bits, 4 DAC channel address bits, and 16 data bits.

Table 1.

DAC data bits

2.3 Verification using Zynq

Zynq is a chip that combines an ARM Cortex-A9 processor based on Xilinx 7-series FPGA architecture and FPGA logic fabric. It is widely used in systems that combine FPGA and ARM, and has the advantage of being able to be verified by constructing the Programmable Logic(PL) area and Processing System(PS) area separately. It is a multi-channel bus called Advanced eXtensible Interface(AXI), enabling data communication between PS and PL areas using a bus optimized for read and write[4][5].

4.1 ADC IP

As seen in the overall system structure in Fig. 1, ADC IP has two interfaces[10], ADC0 and ADC1, and has a protocol as shown in the Table 2 to control them through AXI. The interrupt is recognized by the PS as a signal that reading and storing data has been completed. The run mode is determined depending on the protocol settings, and there are a method to read and save data only once and a method to read and save data 1,000 times. The data has a size of 16 bits, and dual port RAM is used to store it. When reading from the ADC only once, the data is stored at address 0, and when new data is applied, address 0 is overwritten. Depending on the setting mode, when data 1,000 is read and saved from the ADC, the data is stored in addresses 0 to 999. Since the stored data is read in 32-bit size through AXI, taking this into account, the two data are combined and stored as one data. Once the storage cycle for each execution mode is complete, it terminates by writing a '1' to the COMPLETE bit of the protocol.

Table 2.

ADC IP protocol

Fig. 2 shows the flowchart of ADC operation. When power is applied and the RUN signal is applied through AXI, the data read from the ADC is read and stored. At this time, check whether the run mode is 1 or 1,000, and if the mode is 1, repeat this 1,000 times. When the process of saving data read from the ADC is completed 1,000 times, or when the mode is 2 and data storage is completed, ‘1’ is written to the complete bit of the corresponding ADC defined in the register map and an interrupt is generated.

Fig. 2.

Flowchart of ADC operation

The interrupt is checked in the PS area, the complete bit of the corresponding ADC is initialized to '0', and the interrupt is cleared. Additionally, the data is specified as a parameter so that the user can control the number of 1,000 occurrences of data in the IP.

4.2 DAC IP

In the case of DAC IP, IP is used in audio, speakers, etc. used in the vehicle's analog output. As shown in Fig. 1, DAC IP has three DAC interfaces[11], and each interface transmits data to the DAC IC through SPI. The DAC IC used in this paper has four channels, and the sequence is configured to sequentially update data on channels 0 to 3. The data has a structure in which it is loaded and transmitted from BRAM.

Table 3 shows the protocol of DAC IP. The first address contains 16-bit data for self-test in the upper bit, and determines whether to export self-test data or data suitable for the DAC mode depending on the operating mode. In DAC mode, there are different types of amplitude, phase, and frequency required in the output analog waveform. Once the desired mode is determined, the data starting point, frequency, and amplitude appropriate for the output are determined, and data is loaded from BRAM according to the corresponding values. BRAM contains all data and has a structure that loads by setting address values according to the situation. The second to fourth addresses in Table 3 are used to output the temperature and air quality used outside and inside the vehicle. Data is written to the lower 16 bits, and is output consistently when a value is written to the 16th bit.

Table 3.

DAC IP protocol

Fig. 3 shows the DAC flowchart. The mode is selected and the self-test is checked. If it is not in the self-test mode, data is exported according to the mode, and after outputting the 0th channel, change the DAC channel command in Table 1 and output to the next channel. This sequence is output to all four channels and then ends. The output of each channel can be set to be the same, and different outputs are also possible. If it is the self-test, print the data in the self-test and check it in the self-test mode.

Fig. 3.

Flowchart of DAC operation

Fig. 4 shows a portion of the output by DAC mode. The IP is designed to change the way the data address value is read depending on the setting mode, and the frequency changes accordingly.

Fig. 4.

Example of output by DAC mode

4.3 DI/O IP

DI/O IP is used to control the digital input and output of the vehicle. This includes vehicle lamps, display output, vehicle buttons, etc. As shown in Fig. 1, the IP is consisted an IP with 10 input buttons and only 1 output. Considering that the vehicle's input button is turned on/off by pressing, there are 8 general input buttons, and there are cases where certain buttons, such as the air purification mode, change the mode depending on the time the button is pressed. Therefore, the two digital input buttons are designed to count data for the time they are pressed. Table 4 shows the DI/O protocol. The first address is largely composed of three parts. Among the 10 inputs, it is divided into an input part that indicates the input state that does not use counting, an output part that activates data output, and an interrupt part that occurs when the input changes. In the case of the interrupt part, the posedge, negedge of the 8 input buttons, and negedge of the count input are checked, and when an interrupt occurs, the corresponding bit is set to 1.

Table 4.

DI/O IP protocol

Fig. 5 shows an example of an interrupt occurring when a digital input is applied.

Fig. 5.

Example of interrupt generation for digital input

In this timing diagram, In1, In2, and In3 represent typical inputs, and In9 represents the count input. An interrupt occurs when the general input is turned on and off, and the count input occurs only once when the count value is saved when the count input is turned off. A total of 10 interrupt signals are delivered to the PS as one interrupt output signal through OR operation.

4.4 Self-test IP

The self-test IP is an IP used to check whether the functions of the DAC and ADC IP mentioned in the previous system are operating properly and has the structure shown in Fig. 6. Two ADC interfaces are recycled and configured, and two DAC interfaces are newly configured to check operation. Data is transmitted through SPI, like existing ADC and DAC. The self-test IP is used to verify the mode using the protocol. The protocol is shown in Table 5. Two addresses represent the operation and data of DAC0 and DAC1, and the other two addresses represent the data, execution, and completion of ADC0 and ADC1. One address value represents digital data output. Using the 20 ports of this IP's data output, the enable signal and select signal are determined for the four mux. Data output from the existing DAC IP is transmitted to the DAC IC, and the four channel data output from the IC is applied to the mux. Data that has passed through the mux is input to the ADC IC through the data output of the self-test. The data is read by the self-test ADC IF, and the data stored in the registry map is compared with the data written by the DAC to check whether the correct data has been transmitted.

Fig. 6.

Self-test IP and verification structure

Table 5.

Self-test IP protocol

In the opposite case, if you extend the data to the DAC interface of the self-test and output it through the run bit, the data will be transmitted to the DAC IC through SPI. The IC's channel output is linked to MUX, and the data received from the ADC IP is checked.

5.1 Verification of ADC IP

To verify ADC IP, voltage is applied to the ADC IC using a power supply, and the output digital value is confirmed through PS. In order to check the precision, the data is judged by looking at the output digital value as the average value once and 1,000 times. Table 6 shows the read data values, which are graphed in Fig. 7. It can be seen that the data increases linearly, and the data for one operation and the average data for 1,000 operations have similar values. The voltage used in the IC is 0 to 10.24 volts, and when a voltage of 10.5 volts was applied, it was confirmed that the maximum value of 32,767 was obtained in two tests.

Table 6.

ADC input data value

Fig. 7.

Verification result graph of ADC IP

5.2 Verification of DAC IP

Data read from Zynq's BRAM is passed to the DAC IC, which transmits SPI communication. The transmitted data is output through the IC, and the output waveform of each mode is checked using an oscilloscope. Fig. 8 shows part of the waveform of mode 1. Shows the output waveforms of two different phases. Here, the vertical sensitivity of channel 1 is 2V, and the vertical sensitivity of channel 2 is 5V. Fig. 9 shows the output waveform of mode 2, showing a waveform with different amplitude and phase than Fig. 8. Table 7 displays values for the DAC output waveform. The reference phase is 0 degrees, and the phase is output differently depending on the mode selection value, confirming normal operation.

Fig. 8.

Oscilloscope output waveform in mode 1

Fig. 9.

Oscilloscope output waveform in mode 2

Table 7.

Summary of output values by mode