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Modern semiconductor CMOS technologies advance over decades and current integrated circuits (ICs) have higher integration densities thanks to the nano-scaled technology. In this CMOS technology, switching currents consumed by the simultaneous switching activities which are synchronized by a global clock have been increased continuously. In addition, the supply voltages for the logic cores inside the ICs have been scaled down to meet low power requirements. As a result, the timing margins of digital circuit designs using those ICs become narrower and smaller. In consequence, the supply voltage variations in the ICs are more critical to the their correct functionality than ever before.

Recently, some FPGA (Field Programmable Gate Array) architectures allow circuit designers to define valid temperatures, and voltage values in the constraints to guide the tool generate the timing models. Nevertheless, not all architectures support this option. Instead, in general, they use a default value which is valid in a typical working condition within the range of 5% of the supply voltage variation to generate parasitic parameters of circuits such as cell delays and interconnection delays for the timing analysis of the best and worst cases [1]. Thus, we can know how much the performance of the target circuits is degraded only within this range of the variations.

In order to make our target circuit become more reliable, we need to put more timing margins for the safety of the circuit operations in the modern semiconductor nanometer technologies where electromagnetic interferences (EMI) and noises are more likely to affect the reliability of digital circuits [2][3]. However, how much the margin is enough to guarantee the functional correctness of ICs? To identify such a margin under supply voltage variations, a supply voltage sensor will be necessary to sniff the voltage variations when the circuits operate in the critical case. Based on the upper and lower bound of voltage variation, we can establish the margins for the circuits.

Typically, a conventional ring oscillator (RO) can be used to detect the supply voltage variations thanks to the relationship between the supply voltage and the cell delay [4]. However, the conventional RO only detects the average voltage variations during a long period of time. A real-time supply voltage variation sensor using a gated RO was proposed in [5]. Nevertheless, their circuits are more suitable for ASIC based designs than an FPGA based designs since their full-custom cells were designed and utilized to obtain fine-grained delay resolutions.

Another type of a supply voltage sensor using a “delay line”, which is called “time digital converter” (TDC), was proposed in [6]. The voltage variations can be detected cycle-by-cycle with the voltage resolution of 29mV. An ASIC version of the sensor in [4] had a finer voltage resolution of 3.9mV [7].

Our supply voltage sensor is made up by using standard Look-up Table (LUT) cells, and dedicated high-speed carry cells. The experiments show that the voltage resolution of our supply voltage sensor is about 3.3mV on a Xilinx FPGA Spartan-6 (XC6SLX9).

For commercial FPGAs such as Xilinx Spartan-6s or other high-end FPGA families, as we mentioned in Section II, they have dedicated CARRY4 chains with very small carry propagation delays in order to support high speed arithmetic logics. The CARRY4 cell is actually a 4-bit carry generation circuit which is implemented with a dedicated carry propagation wire path. The measured propagation delay of one CARRY4 cell is about “134ps”. Note that this delay includes the delays of short wires that are used for configuring CARRY4 cells when measuring the delay. On average, each carry cell inside a CARRY4 cell has a propagation delay of “33.5ps” (= 134ps / 4) since each CARRY4 has four cascaded carry cells.

We can take advantage of the high-speed carry propagating logics to construct a delay chain or a delay line for obtaining fine-grained delay elements.

However, if we only use the dedicated CARRY4 chain, then the length of the delay chain will be prolonged and the corresponding chip area will be large accordingly. Besides, instead of increasing the clock period to increase the accumulated delay changing, we can use larger delay cells such as LUTs as coarse-grain delay elements in order to sense the voltage variations.

Therefore, we propose a delay chain with two parts with two different delay granularity: the first part consists of delay elements implemented by LUT primitives on an FPGA for controlling coarse-grained delay step, and the second part consists of delay elements based on the dedicated fast CARRY4 cells for controlling fine-grained delay step. The detailed structure of such a delay chain is illustrated in Fig. 1.

Fig. 1. 
Schematic of a supply voltage sensor

As shown in Fig. 1, the initial part of the delay chain is composed of LUT primitives and the second part of the chain consists of CARRY4 cells.

In our sensor, a stable clock signal event, which is generated by a Phase Locked Loop (PLL), is propagated over the delay chain, and also used to clock for FFs to capture the values of delay elements’ outputs. At the nominal supply voltage level, the total propagation delay of the sensor is nearly fitted in a half of clock cycle. The falling edge signal of a clock is propagated over the delay chain and stable values at each delay cell are captured into FFs when the clock rises.

Depending on the signal propagation speed over the delay chain which is proportionally affected by the operating supply voltage, the captured values at the FFs show a specific “000...000111...1” pattern. Most of the initial FFs near at the input side capture bit-0s while later FFs located at the end of the sensor capture bit-1s as shown in Fig. 1. From the pattern, the speed of the signal propagation can be detected by checking where is the “0 to 1” transition in the pattern. Earlier “0 to 1” transition in the pattern means slower propagation speed while later “0 and 1” transition means faster propagation speed. Finally, the corresponding operating supply voltage at the speed is derived by looking up a pre-made the pattern to supply voltage mapping table. The calibration table content is given in Table. 1.

This paper presents the design of a high-resolution supply voltage sensor that can be synthesizable on an commercial FPGA. We have verified its functionality, and used it to detect a given voltage drop profile of our target design. All the implementations have been carried out on the Xilinx Spartan-6 (XC6SLX9). The obtained voltage resolution is about 3.3mV thanks to the fine-grain delay resolution we have with dedicated high-speed CARRY4 cells in the FPGA. Compared to the previous work in [6][7], [9]-[11], our voltage sensor has a better sensing resolution.

The proposed method can be effectively employed and used in the highly reliable digital circuits that are used in a safety-critical system working in a harsh and noise environment such as a cruise-control system of an airplane and an airbag control systems in a car.