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Fig. 4 shows the basic state and control part of the register map. The Channel Software Reset in Fig. 4 is used to reset each of the eight multiple channels. As shown in Fig. 5, if the 15th to 8th data bits are set to 1, a software reset is performed for each channel. When software resets, the counter values of individual channels, control registers, and FIFO buffers are cleared. Using software reset is also useful for initializing in case of an existing malfunction.

Fig. 4. 
State and control part of the register map

Fig. 5. 
Details of channel software reset

In the case of Start Convert & FIFO Full status in Fig. 6, there are two functions. When 7~0 of data bits are set to 1, conversion of individual channels is started. After each data is corrected and stored in a register, the data is transmitted through SPI communication. However, in order to transmit a channel, the FIFO register of each channel must be set.

Fig. 6. 
Detailed view of start convert & FIFO full status

In fact, channel conversion starts at least 6.625us after the Start Convert bit is set, but it is stable to set it to proceed after 10us. The register is also used to indicate the FIFO status of the currently used channel. In this case, the set bit of each channel indicates that the data is full, and data transmission is not approved. Data transfer here refers to writing additional data in the CPU. It is important to avoid writing additional data to the FIFO buffer because data transfer may not be acknowledged and a system bus error may occur. In the case of the register in Fig. 4, it is designed so that data can be written in 16 bits or 8 bits. The entire state is cleared upon software or hardware reset.

In the Interrupt Status of Fig. 7, data bits 15~8 indicate the interrupt status. The interrupt condition of each channel occurs when the data of the FIFO is smaller than the set reference value. In case of interrupt, it can be turned on or off through the interrupt enable signal.

Fig. 7. 
Details of Interrupt status

In the case of the Interrupt Vector in Fig. 8, it can be used as a pointer in the routine handling interrupt. The size of the vector is 8 bits, as allocated by the register map, and can be used to point to one of 256 locations.

Fig. 8. 
Interrupt Vector

The data related to the calibration coefficient of the register map in Fig. 9 is used to fetch the data stored in EEPROM and correct the FIFO data.

Fig. 9. 
Calibration factor memory in register map

The calibration steps can adjust and improve the accuracy of the uncalibrated data sent by the software. There is a unique offset and gain correction factor for each channel, which helps with data correction. The existing method determines whether to read or write data to the data of address 04 and puts the address value. Depending on the value to be read or written, the data in address 05 is written or the data stored in number 06 is displayed. Since this method has to go through the EEPROM, there is a disadvantage in that it is slow in transmitting and receiving data. To compensate for this, the RAM was configured to read or write data directly. The data correction method is as in Eq. 1.

The input data used to derive the "result" in Eq. 1 is as follows. In Eq. 1, Data refers to the value input from the CPU, which is software. In the case of gain, it refers to the value obtained by dividing the error value of the gain stored in the memory by the value of 262,144. Offset refers to the value obtained by dividing the offset error value stored in the memory by 4. Volts vary depending on the range of voltage used. If the voltage used is polarity, -5V to +5V, it has a value of 0, but if it is unipolar, 0 to 10V, it has a value of 32,768.

The channel register of the FIFO is shown in Fig. 10. It is composed of 8 channels, and each channel has 4 sections of FIFO, and is equally composed of registers related to control / status, DAC interval, and FIFO buffer. Through this, each channel can operate in a setting independent of other channels. Each section consists of an 8-bit control status register, an 8-bit timer prescaler, a 16-bit conversion timer and a 16-bit FIFO buffer.

Fig. 10. 
Channel registers in FIFO

The status and control registers are used to indicate the status of the FIFO as shown in Fig. 11. Bit 0 indicates the empty state of the FIFO. Bits 2~1 determine whether to use FIFO, single mode, continuous mode, or whether to use external trigger input when outputting FIFO. Bit 3 is used to select whether to use as input or output when using an external trigger. Bit 4 determines whether the corresponding channel uses interrupt. Bits 6~5 determine whether to generate an interrupt when the number of data in the current FIFO is less than how many data are present in the FIFO Since there are 2 bits, 4 can be selected, and either not used, or 4, 16 or 64 can be selected. Bit 7 is not used.

Fig. 11. 
Detailed view of status and control registers

In the case of the timer prescaler in Fig. 12, it is used together with the conversion timer. Here, in the case of the timer prescaler, the hexadecimal value of 35 is the minimum value. If a value smaller than this is applied, there is a risk of malfunction. When this is applied, conversion starts at 6.625us intervals, which can achieve a speed of about 150KHz. When converting to 150KHz, the conversion accuracy is lowered, so the recommended conversion speed for the existing module is 100KHz.

Fig. 12. 
Detail view of timer prescaler and conversion timer

That is, 10us is recommended. Eq. 2 is used to calculate this value, where the unit of the calculated value is microsecond.

Based on the input 8MHz clock, the value of the timer prescaler and the conversion timer value are multiplied, and the conversion time is obtained by dividing by 8. Here, the range of the timer prescaler value has a decimal value of 53~255 as mentioned in the register map, and the range of the conversion timer value has as much as 1~65,536 data. Using Eq. 2 when the timer prescaler value is 53 and the conversion timer value is 1, a value of 6.625us is derived, but the minimum value is redefined as 10us because the conversion accuracy is poor. To this end, the initial value is set when the value of the timer prescaler is 80 and the timer value is 1.

Each channel has a dedicated FIFO buffer that can hold 128 samples of data. FIFO data is used for data transmission, and the size is 16 bits. When starting to write new data, care must be taken not to full the FIFO. If there are 128 samples of data in the FIFO, additional data should not be written. Writing additional data may cause an error. To avoid this error, you can read the FIFO Full flag bit before writing the FIFO. A software or hardware reset can also be implemented to clear the FIFO.

As mentioned earlier, it is good practice to enable interrupts through the threshold of interrupts when the FIFO is almost empty. When interrupt occurs, the number of new data should be written to the FIFO by subtracting the existing threshold from the total number of data. Any remaining addresses are not used.

The structure of the whole system is shown in Fig. 13. CPU, Spartan 3A, and DAC chip exist in the whole system. The CPU is used to change the initial values of various register maps and FIFO settings, or to perform status and control. The internal structure of FIFO is configured as shown in Fig. 14. It also serves to supply data when an interrupt occurs. In Spartan 3A[15][16], there is a bus system and register map to communicate with the CPU mentioned above, and an SPI module for communicating with FIFO and DAC of 8 channels. In order to operate 8 channels independently, it is used to transmit data to the DAC using the associated register map and 1 SPI communication that can set the mode and data transmission period of 1 FIFO per each channel.

Fig. 13. 
Structure of overall system

Fig. 14. 
FIFO configuration diagram

The flowchart of the algorithm is shown in Fig. 15. When the system power is applied and clock and reset are applied, the system operates. According to the flowchart, it is judged whether there is data in the FIFO, and if it is not Full, the data is stored in the FIFO in order. If all 128 samples of data are saved, no additional data is saved. When the Start Convert signal of each channel is generated, the data is sequentially retrieved from the FIFO and the data is corrected. The corrected digital data is stored in the FIFO Port of the FIFO register of each channel. When outputting data, it loads and outputs data from the aforementioned FIFO Port.

Fig. 15. 
Algorithm flowchart

Two main modes are used to output data, single mode and continuous mode. The single mode is a structure that outputs the last pointer value of the FIFO whenever the Start Convert signal occurs. In the continuous mode, when the Start Convert signal is generated, the FIFO pointer value is incremented by 1 at regular intervals to sequentially export data. In the case of single mode, since only single data is used, a specific voltage value is displayed by outputting only the data value when outputting. In the continuous mode, since continuous data is output, a sine wave or other waveform is output.

In the case of SPI, data is exchanged between one master and several slaves, but in this system, there is no reason to return the digital data output to the DAC, so the MISO (Slave Output Master Input) pin is removed. Other signals such as SCLK, MOSI (Master Output Slave Input), SS (Slave Select) or CS (Chip Select) are used. Due to the characteristics of the DAC chip, when outputting data, the data is transferred using SPI communication, and the data is transferred while making the LDAC (Load DAC) signal of each channel LOW. SPI period setting is determined by calculating the values ​​of Timer Prescaler and Conversion Timer of the FIFO register of each channel. In this case, it is a multiplication structure, but an operation is performed using a double counter.

When performing SPI output, additional correction is required for the corrected data. If the output range of ADC is positive, it helps to output positive data by adding the value of 16384.

As illustrated in Fig. 16, the interrupt of each channel checks whether the interrupt is enabled.

Fig. 16. 
Flowchart of interrupt generation

If it is enabled, it proceeds to the step of comparing whether the number of samples is greater or less than the currently set threshold value. If the number of samples is smaller than the set threshold, the corresponding channel generates an interrupt and requests data from the CPU. When an interrupt request occurs, the CPU supplies data.

The experimental environment is as follows. The FPGA used was Spartan3A, and for the DAC module, 8 DAC7731EC chips were used. As mentioned earlier, the SDI pin is present, but the SDO pin is not used.

Design the FIFO and verify the results through simulation. The simulation situation is as follows. Interrupts are enabled and the threshold is 64. Looking at the result in Fig. 17, if the current sample value is less than 64, a signal called o_th is generated, and this signal generates an interrupt.

Fig. 17. 
Result of Interrupt generation simulation

Fig. 18 shows the simulation result of SPI communication. If the output data is 1000_0100_1101_1110, when the count value of SPI sequentially decreases from MSB to LSB at signal timing, data is output to SDI.

Fig. 18. 
Results of SPI communication simulation

Fig. 19 shows the final result waveform. In the experimental environment, the same data was input to only two channels and operated in continuous mode. At the beginning of the experiment, the signal was distorted after a certain period of time in the data output, but it was identified as a problem with the generation period of the SPI output and was corrected.

Fig. 19. 
Measurement of DAC data output waveform