[ Article ]
The Journal of Korean Institute of Information Technology - Vol. 19, No. 8, pp.59-65
ISSN: 1598-8619 (Print) 2093-7571 (Online)
Print publication date 31 Aug 2021
Received 23 Jun 2021 Revised 13 Jul 2021 Accepted 16 Jul 2021

A High Precision, Wide Operating Range Charge Pump Circuit in a Phase Locked Loop for a CMOS Image Sensor

Jimin Cheon*
*Professor, School of Electronic Engineering, Kumoh National Institute of Technology

Correspondence to: Jimin Cheon School of Electronic Engineering, Kumoh National Institute of Technology, 61 Daehak-ro, Gumi-si, 39177 Korea Tel.: +82-54-478-7436, Email: jimin.cheon@kumoh.ac.kr

Abstract

This paper proposes a charge pump(CP) with high precision and wide operating range used in a phase locked loop(PLL) in a CMOS image sensor(CIS). It can reduce the current mismatch phenomenon for the PLL generating the clock of a CIS, while maintaining wide operating range. In the CP circuit, the current mismatching characteristics and operating range are affected by the performances of the current source in the CP circuit. The proposed CP circuit is embodied with current mirror bias circuits for wide operating range and current source circuits of regulated cascode structure for high output impedance in order to reduce current mismatch with wide operating range. The proposed high precision, wide operating range CP circuit is fabricated as a chip in a 350 nm CMOS process, and the characteristics of current matching are measured in the Keithly source measurement unit. The operating range of the proposed CP circuit is 2.7 V, and the maximum current mismatch is 0.31% and the maximum current deviation is 0.19%.

초록

본 논문에서는 CMOS 이미지 센서(CMOS image sensor, CIS)의 위상 고정 루프(phase locked loop, PLL)에 사용되는 넓은 동작 범위를 가지면서 동시에 높은 정밀도를 가지는 전하 펌프(charge pump, CP) 회로를 제안하였다. 제안된 CP 회로는 넓은 동작 범위를 유지하면서 CIS의 메인 클럭을 생성하는 PLL의 전류 불일치를 줄일 수 있다. CP 회로에서 전류 불일치 특성과 동작 범위는 CP 회로의 전류원 회로의 성능에 의해 결정된다. 제안된 CP 회로는 넓은 동작 범위에서 전류 불일치를 줄이기 위해 넓은 동작 범위를 위한 전류 미러 바이어스 회로와 높은 출력 임피던스를 위한 레귤레이티드 캐스코드 구조의 전류원 회로로 구현된다. 제안된 높은 정밀도와 넓은 동작 범위를 가지는 CP 회로는 350nm CMOS 공정을 사용하여 칩으로 제작되고 전류 정합 특성은 Keithly 소스 측정 장치를 사용하여 측정되었다. 제안된 CP 회로의 동작 범위는 2.7V이고 최대 전류 불일치는 0.31%, 최대 전류 편차는 0.19%로 측정되었다.

Keywords:

charge pump, current mismatch, high precision, wide operating range, PLL, regulated cascode, current mirror

Ⅰ. Introduction

Recently, as the demand for high-resolution images in mobile imaging increases, the pixel pitch of a CMOS image sensor(CIS) has been reduced to 0.7μm [1][2]. When the pixel pitch decreases, the amount of incident light decreases, making it difficult to secure the signal-to-noise ratio(SNR) of an image in a low-light environment. Therefore, a recent CIS provides various binning modes that improve sensitivity and SNR by merging some surrounding photodiodes in low-light condition[3][4].

Since the resolution and frame rate of the CIS vary according to the binning mode conditions provided, a wide range of the speed of a main clock used for the CIS is also required. Therefore, a phased locked looop (PLL) circuit of the CIS must be able to generate the main clock in a wide frequency range[5].

The PLL circuit which generates the clock inside the CIS widely uses a charge pump(CP) PLL structure that can easily implement high-speed, low jitter, and wide locking range characteristics[6]. The role of the CP in the PLL is to inject or remove current from the loop filter(LF) to implement the integral operation. One of the key design challenges is to minimize the current mismatch between charge and discharge currents, i.e. current sink and current source. Another design issue, especially in a wideband PLL, is the output voltage headroom of the current source used to implement the CP. To achieve the widest possible clock frequency range, the CP output voltage should ideally remain in the range from ground to the power supply rail. It takes full advantage of the oscillator's tuning range while maintaining current source operation and current invariance.

Therefore, this paper proposes a CP circuit with high precision and wide operating range while decreasing the current mismatch phenomenon for the PLL which generates the clock of the CIS with various binning modes.

Ⅱ. CP Circuit

2.1 CP PLL and Characteristics of CP Circuit

Fig. 1 shows the block diagram of the CP PLL and the schematic diagram of the single-ended CP circuit that is most suitable architecture of the CP for the PLL when considering system flexibility, low power consumption, and silicon area[7]-[9] and the LF circuit.

Block diagram of CP PLL and schematic diagram of CP and LF circuits

After receiving the phase difference signal outputs, UP and DN, from the phase frequency detector(PFD), the CP circuit charges or discharges the capacitor of the LF with a constant current during the phase difference signal width to generate the voltage signal, VCP, and send it to the voltage controlled oscillator (VCO).

The current mismatch and the output voltage headroom of the CP circuit are affected by the output impedances, RUP and RDN, and the voltage headrooms, ΔVHRP and ΔVHRN, of the current sources, IUP and IDN constituting the CP circuit. To design the CP circuit with high precision and wide operating range, IUP and IDN should be designed so that the smaller the ΔVHRP and ΔVHRN, the larger the RUP and RDN[5].

2.2 Conventional CP Circuit

Fig. 2 shows the conventional CP circuit using a cascode current source with a current mirror bias circuit with wide operating range[5]. This structure has high output impedance to minimize current mismatch while having wide operating range by minimizing voltage headroom.

Conventional CP circuit implemented and V-I relationship[5]

The output impedances, RUP and RDN, of the current sources IUP and IDN are obtained by using the impedance reflection rule[10] as follows.

 (1)

Here, gm,MUP2 and gm,MDN2 are transconductances of MUP2 and MDN2, respectively. Also rds,MUP2, rds,MUP1, rds,MDN2, and rds,MDN1 are small-signal equivalent resistances between drain port and source port of MUP2, MUP1, MDN2, and MDN1, respectively.

Since the CP circuit uses the current mirror bias circuit with wide operating range, its operating range, ΔVCP_Swing is obtained as follows[10].

 $\begin{array}{c}\Delta {V}_{HRN}\le \Delta {V}_{{CP}_{-}Swing}\le {V}_{DD}-\Delta {V}_{HRP}\hfill \\ \Delta {V}_{HRN}={V}_{OV,MDN1}+{V}_{OV,MDN2},\hfill \\ \Delta {V}_{HRP}={V}_{OV,ΜUP1}+{V}_{OV,ΜUP2}\hfill \end{array}$ (2)

Here, VOV,MDN1, VOV,MDN2, VOV,MUP1, and VOV,MUP2 are overdrive voltages of MDN1, MDN2, MUP1, and MUP2, respectively.

2.3 Proposed CP Circuit

Fig. 3 shows the proposed high precision, wide operating range CP circuit. By applying the regulated cascode structure composed of the operational transconductance amplifiers(OTAs), OTAN and OTAP, RUP and RDN of IUP and IDN increase when compared to Eq. (1) as follows[10].

 (3)

Proposed CP circuit implemented and V-I relationship

Note that AOTAN and AOTAP are DC gains of OTAN and OTAP, respectively.

Although the regulated cascode structure is used, the operating range of the CP circuit is the same as Eq. (2)[10].

Ⅲ. Experimental Results

3.1 Simulation results

In order to verify the comparison between the conventional CP circuit and the proposed CP circuit, some simulations are performed using 350 nm CMOS process. Here, the MOSFET sizes of the current mirror bias circuit and the current source circuit are determined as LP=0.35 μm, WP=90 μm (18 μm, m=5), LN=0.45 μm, WN=30 μm (6 μm, m=5). The power supply voltage was VDD=3.3 V and ICP=100 µA. To implement the regulated cascode architecture for the proposed CP circuit, OTAN and OTAP are designed as the differential pair with 5 transistors so that AOTAN and AOTAP are 30 V/V.

Fig. 4 shows the simulated IUP and IDN graphs while changing the VCP voltage of each CP circuit. While the magnitude of ΔVCP_Swing of the two CP circuits is the same as 0.4 V, it can be seen that the current sources of the proposed CP circuit have a larger output impedances than those of the conventional CP circuit from the slope of the zoomed-in figures.

V-I relationship of CP circuits (X-axis : VCP, Y-axis : IUP & IDN)

Fig. 5 shows the current matching characteristics, IMIS=IUP-IDN, between IUP and IDN according to VCP change obtained by setting UP=1 (UPb=0) and DN=1 (DNb=0) and performing DC analysis on VCP node. From the zoomed-in graph, it can be seen that the IMIS of the proposed CP circuit is more improved than that of the conventional CP circuit. Considering ΔVCP_Swing=2.5 V, the proposed CP circuit has the maximum current mismatch of 0.22% and the maximum current deviation of 0.17% whereas the conventional CP circuit has the maximum current mismatch of 3.84% and the maximum current deviation of 1.97%. Table 1 shows the summary of the simulation results for CP circuits.

Current matching characteristics of CP circuits (X-axis : VCP, Y-axis : IMIS=IUP-IDN)

Summary of simulation results for CP circuits

3.2 Measurement result

Fig. 6 shows the microphotograph of the chip fabricated in 350 nm CMOS process. The power supply voltage is 3.3 V and ICP is 100 μA.

Microphotograph of fabricated chip

The fabricated chip is measured using the source measurement unit of Keithley and the current matching characteristic graph of the CP circuit is obtained as shown in Fig. 7. When ΔVCP_Swing=2.7 V, the maximum current mismatch is 0.31% and the maximum current deviation is 0.19%.

Measured current matching characteristics of proposed CP circuit

Ⅳ. Conclusion

In this paper, we proposed the CP circuit with wide operating range while decreasing the current mismatch for the CP PLL generating the clock of the CIS. The operating range and current mismatch of the CP circuit are affected by the characteristics of the current source constituting the CP circuit. The proposed CP circuit is embodied with current mirror bias circuits for wide operating range and current source circuits of regulated cascode structure for high output impedance in order to reduce current mismatch with wide operating range.

The proposed high precision, wide operating range CP circuit is fabricated in a 350 nm CMOS process, and current matching characteristic is measured in the Keithley source measurement unit. The power supply voltage is 3.3 V and the ICP of the CP circuit is 100 μA. The proposed CP circuit has ΔVCP_Swing=2.7V, where the maximum current mismatch is 0.31% and the maximum current deviation is 0.19%.

Acknowledgments

This research was supported by Kumoh National Institute of Technology (2018-104-129).

References

• H. Kim, J. Park, I. Joe, D. Kwon, J. H. Kim, D. Cho, T. Lee, C. Lee, H. Park, S. Hong, C. Chang, J. Kim, H. Lim, Y. Oh, Y. Kim, S. Nah, S. Jung, J. Lee, J. Ahn, H. Hong, K. Lee, and H.-K. Kang, "A 1/2.65in 44Mpixel CMOS Image Sensor with 0.7µm Pixels Fabricated in Advanced Full-Depth Deep-Trench Isolation Technology", 2020 IEEE International Solid-State Circuits Conference, pp. 104-106, Feb. 2020. [https://doi.org/10.1109/ISSCC19947.2020.9062924]
• J. Park, S. Park, K. Cho, T. Lee, C. Lee, D. Kim, B. Lee, S. Kim, H.-C. Ji, D. Im, H. Park, J. Kim, J. Cha, T. Kim, I.-S. Joe, S. Hong, C. Chang, J. Kim, W. Shim, T. Kim, J. Lee, D. Park, E. Kim, H. Park, J. Lee, Y. Kim, J. Ahn, Y. Hong, C. Jun, H. Kim, C.-R. Moon, and H.-K. Kang, "1/2.74-inch 32Mpixel-Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation", 2021 IEEE International Solid-State Circuits Conference, pp. 122-124, Feb. 2021. [https://doi.org/10.1109/ISSCC42613.2021.9365751]
• Y. Oh, M. Kim, W. Choi, H. Choi, H. Jeon, J. Seok, Y. Choi, J. Jung, K. Yoo, D. Park, Y. Kim, K.-M. Koh, J. Lee, C.-R. Moon, and J. Ahn, "A 0.8 μm Nonacell for 108 Megapixels CMOS Image Sensor with FD-Shared Dual Conversion Gain and 18,000e- Full-Well Capacitance", 2020 IEEE International Electron Devices Meeting, 2020, pp. 16.2.1-16.2.4, Dec. 2020.
• Y. J. Jung, V. C. Venezia, S. Lee, C. Y. Ai, Y. Zhu, K. W. Yeung, G. Park, W. Choi, Z. Lin, W.-Z. Yang, A. C.-W. Hsiung, and L. Grant, "A 64M CMOS Image Sensor using 0.7um pixel with high FWC and switchable conversion gain", 2020 IEEE International Electron Devices Meeting, 2020, pp. 16.3.1-16.3.4, Dec. 2020. [https://doi.org/10.1109/IEDM13553.2020.9371889]
• J. Hwang, Y. Lee, and J. Cheon, "A Charge Pump Circuit in a Phase Locked Loopfor a CMOS X-Ray Detector", Journal of Korea Institute of Information, Electronics, and Communication Technology, Vol. 13, No. 5, pp. 359-369, Oct. 2020.
• H.-J. Seo, S.-H. Han, and T.-W. Cho, "Design of Low-Voltage High-Speed Charge Pump with 900 Operating Frequency for PLL Applications", The Journal of Korean Institute of Information Technology, Vol. 8, No. 2, pp. 9-16, Feb. 2010.
• M. Johnson and E. Hudson, "A variable delay line PLL for CPU-coprocessor synchronization", IEEE Journal of Solid-State Circuits, Vol. 23, No. 10, pp. 1218-1223, Oct. 1988. [https://doi.org/10.1109/4.5947]
• I. A. Young, J. K. Greason, and K. L. Wong, "A PLL Clock Generator with 5 to 110MHz of Lock Range for Microprocessors", IEEE Journal of Solid-State Circuits, Vol. 27, No. 11, pp. 1599-1607, Nov. 1992. [https://doi.org/10.1109/4.165341]
• C. Shan, L. Chen, X. Li, X. Geng, and K. Wang, "A charge pump phase-locked loop with dual-voltage controlled VCO applied to 28nm process FPGA", 2021 IEEE International Conference on Consumer Electronics and Computer Engineering, pp. 171-175, Jan. 2021. [https://doi.org/10.1109/ICCECE51280.2021.9342589]
• D. A. Johns and K. Martin, "Analog Integrated Circuit Design", New York:Wiley, 1997.
Author
Jimin Cheon

2003 : B.S. Degree in School of Electrical and Electronic Engineering, Yonsei University

2005 : M.S. Degree in Department of Electrical and Electronic Engineering, Yonsei University

2010 : Ph.D. Degree in Department of Electrical and Electronic Engineering, Yonsei University

2010 : Visiting Researcher, NHK Science and Technology Research Lab

2010 ~ 2012 : Senior Engineer, Image Development Team, System LSI Business, Samsung Electronics

2012 ~ 2013 : Manager, Semiconductor Tech. Lab, Fusion Technology R&D Center, SK telecom

2013 ~ 2018 : Assistant Professor, School of Electronic Engineering, Kumoh National Institute of Technology

2018 ~ present : Associate Professor, School of Electronic Engineering, Kumoh National Institute of Technology

Research interests : CMOS Integrated Circuits, Precision Analog Circuits, Mixed-Signal Integrated Circuits, CMOS Image Sensors, PCB Design for EMC

Fig. 1.

Block diagram of CP PLL and schematic diagram of CP and LF circuits

Fig. 2.

Conventional CP circuit implemented and V-I relationship[5]

Fig. 3.

Proposed CP circuit implemented and V-I relationship

Fig. 4.

V-I relationship of CP circuits (X-axis : VCP, Y-axis : IUP & IDN)

Fig. 5.

Current matching characteristics of CP circuits (X-axis : VCP, Y-axis : IMIS=IUP-IDN)

Fig. 6.

Microphotograph of fabricated chip

Fig. 7.

Measured current matching characteristics of proposed CP circuit

Table 1.

Summary of simulation results for CP circuits

△VHRN △VHRP △VCP_Swing Current deviation Max. current mismatch
Conventional (Fig. 2) 0.4 V 0.4 V 2.50 V / 75.76%
(2.50 V/3.3 V)
-1.97 μA ~ 1.87 μA 3.84 μA
Proposed (Fig. 3) -0.17 μA ~ 0.05 μA 0.22 μA