A High Precision, Wide Operating Range Charge Pump Circuit in a Phase Locked Loop for a CMOS Image Sensor
*Professor, School of Electronic Engineering, Kumoh National Institute of TechnologyAbstract
This paper proposes a charge pump(CP) with high precision and wide operating range used in a phase locked loop(PLL) in a CMOS image sensor(CIS). It can reduce the current mismatch phenomenon for the PLL generating the clock of a CIS, while maintaining wide operating range. In the CP circuit, the current mismatching characteristics and operating range are affected by the performances of the current source in the CP circuit. The proposed CP circuit is embodied with current mirror bias circuits for wide operating range and current source circuits of regulated cascode structure for high output impedance in order to reduce current mismatch with wide operating range. The proposed high precision, wide operating range CP circuit is fabricated as a chip in a 350 nm CMOS process, and the characteristics of current matching are measured in the Keithly source measurement unit. The operating range of the proposed CP circuit is 2.7 V, and the maximum current mismatch is 0.31% and the maximum current deviation is 0.19%.
초록
본 논문에서는 CMOS 이미지 센서(CMOS image sensor, CIS)의 위상 고정 루프(phase locked loop, PLL)에 사용되는 넓은 동작 범위를 가지면서 동시에 높은 정밀도를 가지는 전하 펌프(charge pump, CP) 회로를 제안하였다. 제안된 CP 회로는 넓은 동작 범위를 유지하면서 CIS의 메인 클럭을 생성하는 PLL의 전류 불일치를 줄일 수 있다. CP 회로에서 전류 불일치 특성과 동작 범위는 CP 회로의 전류원 회로의 성능에 의해 결정된다. 제안된 CP 회로는 넓은 동작 범위에서 전류 불일치를 줄이기 위해 넓은 동작 범위를 위한 전류 미러 바이어스 회로와 높은 출력 임피던스를 위한 레귤레이티드 캐스코드 구조의 전류원 회로로 구현된다. 제안된 높은 정밀도와 넓은 동작 범위를 가지는 CP 회로는 350nm CMOS 공정을 사용하여 칩으로 제작되고 전류 정합 특성은 Keithly 소스 측정 장치를 사용하여 측정되었다. 제안된 CP 회로의 동작 범위는 2.7V이고 최대 전류 불일치는 0.31%, 최대 전류 편차는 0.19%로 측정되었다.
Keywords:
charge pump, current mismatch, high precision, wide operating range, PLL, regulated cascode, current mirrorⅠ. Introduction
Recently, as the demand for high-resolution images in mobile imaging increases, the pixel pitch of a CMOS image sensor(CIS) has been reduced to 0.7μm [1][2]. When the pixel pitch decreases, the amount of incident light decreases, making it difficult to secure the signal-to-noise ratio(SNR) of an image in a low-light environment. Therefore, a recent CIS provides various binning modes that improve sensitivity and SNR by merging some surrounding photodiodes in low-light condition[3][4].
Since the resolution and frame rate of the CIS vary according to the binning mode conditions provided, a wide range of the speed of a main clock used for the CIS is also required. Therefore, a phased locked looop (PLL) circuit of the CIS must be able to generate the main clock in a wide frequency range[5].
The PLL circuit which generates the clock inside the CIS widely uses a charge pump(CP) PLL structure that can easily implement high-speed, low jitter, and wide locking range characteristics[6]. The role of the CP in the PLL is to inject or remove current from the loop filter(LF) to implement the integral operation. One of the key design challenges is to minimize the current mismatch between charge and discharge currents, i.e. current sink and current source. Another design issue, especially in a wideband PLL, is the output voltage headroom of the current source used to implement the CP. To achieve the widest possible clock frequency range, the CP output voltage should ideally remain in the range from ground to the power supply rail. It takes full advantage of the oscillator's tuning range while maintaining current source operation and current invariance.
Therefore, this paper proposes a CP circuit with high precision and wide operating range while decreasing the current mismatch phenomenon for the PLL which generates the clock of the CIS with various binning modes.
Ⅱ. CP Circuit
2.1 CP PLL and Characteristics of CP Circuit
Fig. 1 shows the block diagram of the CP PLL and the schematic diagram of the single-ended CP circuit that is most suitable architecture of the CP for the PLL when considering system flexibility, low power consumption, and silicon area[7]-[9] and the LF circuit.
After receiving the phase difference signal outputs, UP and DN, from the phase frequency detector(PFD), the CP circuit charges or discharges the capacitor of the LF with a constant current during the phase difference signal width to generate the voltage signal, V_{CP}, and send it to the voltage controlled oscillator (VCO).
The current mismatch and the output voltage headroom of the CP circuit are affected by the output impedances, R_{UP} and R_{DN}, and the voltage headrooms, ΔV_{HRP} and ΔV_{HRN}, of the current sources, I_{UP} and I_{DN} constituting the CP circuit. To design the CP circuit with high precision and wide operating range, I_{UP} and I_{DN} should be designed so that the smaller the ΔV_{HRP} and ΔV_{HRN}, the larger the R_{UP} and R_{DN}[5].
2.2 Conventional CP Circuit
Fig. 2 shows the conventional CP circuit using a cascode current source with a current mirror bias circuit with wide operating range[5]. This structure has high output impedance to minimize current mismatch while having wide operating range by minimizing voltage headroom.
The output impedances, R_{UP} and R_{DN}, of the current sources I_{UP} and I_{DN} are obtained by using the impedance reflection rule[10] as follows.
$$$\begin{array}{c}{R}_{UP}\cong {g}_{m,{\rm M}UP2}{r}_{ds,{\rm M}UP2}{r}_{ds,{\rm M}UP1},\hfill \\ {R}_{DN}\cong {g}_{m,{\rm M}DN2}{r}_{ds,{\rm M}DN2}{r}_{ds,MDN1}\hfill \end{array}$$$ | (1) |
Here, g_{m,MUP2} and g_{m,MDN2} are transconductances of M_{UP2} and M_{DN2}, respectively. Also r_{ds,MUP2}, r_{ds,MUP1}, r_{ds,MDN2}, and r_{ds,MDN1} are small-signal equivalent resistances between drain port and source port of M_{UP2}, M_{UP1}, M_{DN2}, and M_{DN1}, respectively.
Since the CP circuit uses the current mirror bias circuit with wide operating range, its operating range, ΔV_{CP_Swing} is obtained as follows[10].
$$$\begin{array}{c}\Delta {V}_{HRN}\le \Delta {V}_{{CP}_{-}Swing}\le {V}_{DD}-\Delta {V}_{HRP}\hfill \\ \Delta {V}_{HRN}={V}_{OV,MDN1}+{V}_{OV,MDN2},\hfill \\ \Delta {V}_{HRP}={V}_{OV,{\rm M}UP1}+{V}_{OV,{\rm M}UP2}\hfill \end{array}$$$ | (2) |
Here, V_{OV,MDN1}, V_{OV,MDN2}, V_{OV,MUP1}, and V_{OV,MUP2} are overdrive voltages of M_{DN1}, M_{DN2}, M_{UP1}, and M_{UP2}, respectively.
2.3 Proposed CP Circuit
Fig. 3 shows the proposed high precision, wide operating range CP circuit. By applying the regulated cascode structure composed of the operational transconductance amplifiers(OTAs), OTA_{N} and OTA_{P}, R_{UP} and R_{DN} of I_{UP} and I_{DN} increase when compared to Eq. (1) as follows[10].
$$$\begin{array}{c}{R}_{UP}\cong {A}_{OTAN}{g}_{m,{\rm M}UP2}{r}_{ds,{\rm M}UP2}{r}_{ds,{\rm M}UP1},\hfill \\ {R}_{DN}\cong {A}_{OTAP}{g}_{m,{\rm M}DN2}{r}_{ds,{\rm M}DN2}{r}_{ds,MDN1}\hfill \end{array}$$$ | (3) |
Note that A_{OTAN} and A_{OTAP} are DC gains of OTA_{N} and OTA_{P}, respectively.
Although the regulated cascode structure is used, the operating range of the CP circuit is the same as Eq. (2)[10].
Ⅲ. Experimental Results
3.1 Simulation results
In order to verify the comparison between the conventional CP circuit and the proposed CP circuit, some simulations are performed using 350 nm CMOS process. Here, the MOSFET sizes of the current mirror bias circuit and the current source circuit are determined as L_{P}=0.35 μm, W_{P}=90 μm (18 μm, m=5), L_{N}=0.45 μm, W_{N}=30 μm (6 μm, m=5). The power supply voltage was V_{DD}=3.3 V and I_{CP}=100 µA. To implement the regulated cascode architecture for the proposed CP circuit, OTA_{N} and OTA_{P} are designed as the differential pair with 5 transistors so that A_{OTAN} and A_{OTAP} are 30 V/V.
Fig. 4 shows the simulated I_{UP} and I_{DN} graphs while changing the V_{CP} voltage of each CP circuit. While the magnitude of Δ_{VCP_Swing} of the two CP circuits is the same as 0.4 V, it can be seen that the current sources of the proposed CP circuit have a larger output impedances than those of the conventional CP circuit from the slope of the zoomed-in figures.
Fig. 5 shows the current matching characteristics, I_{MIS}=I_{UP}-I_{DN}, between I_{UP} and I_{DN} according to V_{CP} change obtained by setting UP=1 (UPb=0) and DN=1 (DNb=0) and performing DC analysis on VCP node. From the zoomed-in graph, it can be seen that the I_{MIS} of the proposed CP circuit is more improved than that of the conventional CP circuit. Considering ΔV_{CP_Swing}=2.5 V, the proposed CP circuit has the maximum current mismatch of 0.22% and the maximum current deviation of 0.17% whereas the conventional CP circuit has the maximum current mismatch of 3.84% and the maximum current deviation of 1.97%. Table 1 shows the summary of the simulation results for CP circuits.
3.2 Measurement result
Fig. 6 shows the microphotograph of the chip fabricated in 350 nm CMOS process. The power supply voltage is 3.3 V and I_{CP} is 100 μA.
The fabricated chip is measured using the source measurement unit of Keithley and the current matching characteristic graph of the CP circuit is obtained as shown in Fig. 7. When ΔV_{CP_Swing}=2.7 V, the maximum current mismatch is 0.31% and the maximum current deviation is 0.19%.
Ⅳ. Conclusion
In this paper, we proposed the CP circuit with wide operating range while decreasing the current mismatch for the CP PLL generating the clock of the CIS. The operating range and current mismatch of the CP circuit are affected by the characteristics of the current source constituting the CP circuit. The proposed CP circuit is embodied with current mirror bias circuits for wide operating range and current source circuits of regulated cascode structure for high output impedance in order to reduce current mismatch with wide operating range.
The proposed high precision, wide operating range CP circuit is fabricated in a 350 nm CMOS process, and current matching characteristic is measured in the Keithley source measurement unit. The power supply voltage is 3.3 V and the I_{CP} of the CP circuit is 100 μA. The proposed CP circuit has ΔV_{CP_Swing}=2.7V, where the maximum current mismatch is 0.31% and the maximum current deviation is 0.19%.
Acknowledgments
This research was supported by Kumoh National Institute of Technology (2018-104-129).
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2003 : B.S. Degree in School of Electrical and Electronic Engineering, Yonsei University
2005 : M.S. Degree in Department of Electrical and Electronic Engineering, Yonsei University
2010 : Ph.D. Degree in Department of Electrical and Electronic Engineering, Yonsei University
2010 : Visiting Researcher, NHK Science and Technology Research Lab
2010 ~ 2012 : Senior Engineer, Image Development Team, System LSI Business, Samsung Electronics
2012 ~ 2013 : Manager, Semiconductor Tech. Lab, Fusion Technology R&D Center, SK telecom
2013 ~ 2018 : Assistant Professor, School of Electronic Engineering, Kumoh National Institute of Technology
2018 ~ present : Associate Professor, School of Electronic Engineering, Kumoh National Institute of Technology
Research interests : CMOS Integrated Circuits, Precision Analog Circuits, Mixed-Signal Integrated Circuits, CMOS Image Sensors, PCB Design for EMC